The present invention relates to a semiconductor chip device, and more specifically, to a device that mimics field thermal mini-cycles to assess reliability due to thermally cycling.
There is a reliability concern of a semiconductor device internal layers cracking, delaminating, and failing external interconnections due to thermal cycling within the internal layers.
Current power management design, as applied to semiconductor devices, results in the creation of a high number of smaller thermal cycles. This type of thermal stress environment, coupled with semiconductor devices including finer ground rules and less robust materials, results in a need to more accurately evaluate the impact of thermal mini-cycles on semiconductor device reliability. Application design has attempted to reduce chip power by designing small power islands on the chip that are controlled by clock gating, voltage islands, and thermal feedback circuits. However, this power island designing creates thousands of mini-cycles and potentially creates a thermal gradient across the chip based on the hot spots of power islands. Generally, the state of the art is unaware of how these types of thermal gradients and mini-cycles affects product reliability of the semiconductor design.
Conventional test techniques involve accelerated thermal stressing where the semiconductor device and the corresponding packaging are cycled through temperature ranges as a total system. This method includes a relatively slow ramp up and ramp down in temperature and does not adequately mimic the thermal environment created by the higher number of localized thermal mini-cycles. Typically, test vehicles have heaters in a metal or interconnect layer to change the chip junction temperature (Tj), but this is not an effective test simulation if an area of concern is a stress area below the heaters, that is, in a different layer than the metal layer.
The embodiments described below provide a test device that more closely emulates the actual operating conditions of the semiconductor structure design cycled in a power management mode that creates heat in the transistor level of the semiconductor chip and allows localized heating/stresses to be created at higher frequencies. Also, sensors that detect the actual junction temperature of the device at a given location of device are provided by embodiments herein rather than one uniform junction temperature across the entire device in a traditional/existing testing methodology.